Monolithic CMOS+photonics vs chiplet integration
Updated: 2026-04-29 Status: ◐ Tradeoff framing draws on industry consensus (OFC / ECOC / IEEE Photonics conference programs, SemiAnalysis coverage); specific cost-per-bit comparisons are flagged ⚠ where not primary-sourced. Cross-references: Fotonix process overview · Fotonix PDK customers · competitors
1. The architectural choice
Every silicon-photonics implementation at the system level resolves an integration question: how do the optical devices (modulators, photodetectors, waveguides) connect to the electronic devices (drivers, TIAs, DSPs) that drive and sense them?
There are three structural answers:
- Monolithic — fab everything on a single die. CMOS transistors and photonic devices share the same wafer flow. GF Fotonix 45SPCLO is the canonical commercial monolithic foundry process; Intel SiPh is the canonical internal-only monolithic.
- Hybrid (in-die / wafer-bond) — fab the photonics on one die / wafer and bond a CMOS die or III-V die on top with through-silicon-via (TSV) or copper-pillar bonds. TSMC SiPh + CoWoS-S is the canonical advanced-packaging monolithic-adjacent path.
- Chiplet (multi-die in package) — fab photonic and electronic dies separately, then co-package them on an interposer or organic substrate using UCIe / xLink / proprietary die-to-die. Ayar Labs TeraPHY is the optical-I/O chiplet exemplar; AMD MI300, NVIDIA Blackwell, Intel Ponte Vecchio are CPU/GPU chiplet exemplars (electronic-only); POET Technologies’ Optical Interposer is a hybrid-flip-chip variant on the chiplet end of the spectrum.
GF Fotonix anchors choice #1. The strategic question is whether monolithic remains the right answer as data rates climb to 200/400/800 Gb/s per lane and as design complexity makes single-die yield a bigger problem.
2. The tradeoff matrix
| Dimension | Monolithic (Fotonix) | Hybrid wafer-bond (TSMC SiPh+CoWoS) | Chiplet (UCIe+optical IO) |
|---|---|---|---|
| Yield ceiling | Limited by aggregate photonic+CMOS die yield; large dies expensive | Higher — CMOS yield independent of photonic yield | Highest — each die fab’d at optimal node, KGD before packaging |
| Process flexibility | Locked to one foundry process (45SPCLO at 45 nm CMOS) | CMOS at any TSMC node (5/3/2 nm) + photonic at custom flow | Each die at its own node — photonic at 90 nm SiPh, CMOS at 3 nm, DSP at 5 nm |
| CMOS performance | Bound by 45 nm class transistors (~300 GHz f_T) | TSMC leading-edge (1+ THz f_T at 3 nm) | Best — leading-edge CMOS + optimized photonic |
| Latency / signal integrity | Best — sub-ps interconnect, zero bond parasitic | Medium — TSV / Cu-pillar parasitic | Worst — UCIe interconnect overhead |
| Power per bit (modulator drive) | Low — short interconnect, integrated termination | Medium | Highest — UCIe drivers + impedance matching |
| BOM cost (high volume) | Lowest at scale — single die, single test, single packaging | Higher — wafer-bond + CoWoS substrate | Highest — multiple known-good-die + interposer + bonding |
| Time to first silicon | Long — every change requires full process validation | Medium — CMOS already validated; photonic on its own line | Shortest — change one chiplet at a time |
| Customer optionality | Lowest — locked to GF process | Medium — TSMC’s CMOS is shared with logic customers | Highest — mix-and-match best-of-breed |
| EO-polymer / TFLN integration | Hard — process constraints from CMOS thermal budget | Easier — photonic die can have its own thermal budget | Easiest — photonic die fully decoupled |
⚠ Quantitative cost-per-bit and yield numbers in this table are industry-consensus framing; specific values vary widely by data rate, die size, and product generation.
3. Where monolithic wins
3.1 Power per bit
The hardest economic constraint at hyperscale AI is modulator drive energy per bit. NVIDIA framed this at GTC 2026 (cited in platform overview) in tokens per watt terms: at 1M GPUs × 6M optics × hundreds of mW per modulator, even a fraction-of-a-watt-per-modulator delta compounds into multi-megawatt savings per AI factory.
Monolithic Fotonix wins on power per bit because:
- The driver-to-modulator interconnect is sub-millimeter on-chip routing, not a bond-wire / TSV / UCIe link
- Termination is integrated, not impedance-matched across a die boundary
- ESD and transient protection are tighter
This is the single biggest structural reason why hyperscalers (Microsoft, Meta, Google) and DSP suppliers (Marvell, Broadcom) keep coming back to monolithic SiPh as the volume answer.
3.2 BOM cost at volume
A single Fotonix die replaces (in the monolithic case): photonic die + driver/TIA die + interposer + bond materials + co-packaging steps. At AI-cluster volumes (hundreds of millions of optical engines per year by 2027-2028), the BOM delta is multi-dollar per port — material at scale.
3.3 Signal integrity
200 Gbps PAM4 requires <1 ps eye-opening jitter at the modulator. Bond-wire and TSV parasitics consume a sizeable fraction of that budget; on-die routing essentially does not. As lane rates climb to 400 Gbps PAM4 (and beyond, including 6-bit-per-symbol coherent at the longest reach), monolithic’s signal-integrity advantage compounds.
4. Where chiplet / hybrid wins
4.1 CMOS process advantage
Chiplet architectures let the CMOS DSP / driver run on leading-edge TSMC nodes (3 nm, 2 nm) while the photonic die runs on a slower, optimized SiPh process. Marvell’s optical-DSP family (Ara, Spica, Petra) already runs on TSMC 5/3 nm — the DSP cannot fit on Fotonix’s 45 nm CMOS.
This is why Marvell uses both: DSP on TSMC, photonic engine on GF Fotonix, pluggable as a multi-die package.
4.2 Best-of-breed materials
If the optimal modulator material is EO polymer (LWLG), TFLN (HyperLight, NLM), barium titanate (research-stage), or plasmonic-organic hybrid (Polariton/Marvell), the chiplet/hybrid path lets each material live on its own die without CMOS thermal-budget tension. The polymer poling step at 185°C, for example, is incompatible with leading-edge CMOS BEOL — a chiplet architecture sidesteps the conflict.
GF’s response is to modify Fotonix to accept EO-polymer slot waveguides as a BEOL step (the LWLG GDSFactory PDK is the productized version of this) — but this is a process accommodation, not a structural advantage of monolithic.
4.3 Yield at very large dies
Fotonix dies for high-channel-count CPO can be many cm² in area, where every mm² adds defect-density risk. Chiplet architectures partition the design into smaller dies that each have higher yield independently, then combine known-good-die in package.
For the largest CPO substrates (Broadcom Tomahawk-Optical, NVIDIA Spectrum-X, Marvell Teralynx), chiplet routing is increasingly attractive — and is one structural reason TSMC’s CoWoS-S / CoWoS-L packaging is winning capacity allocation that GF Fotonix arguably could have captured.
5. The actual market verdict — both paths win
The 2025-2026 evidence is that both architectures are commercially scaling, with workload-dependent winner selection:
- Pluggable transceivers (QSFP-DD, OSFP) at 400 Gb/s and 800 Gb/s — monolithic SiPh dominates (Marvell + Broadcom + Cisco transceivers running on GF Fotonix or Tower PH18); BOM cost is binding constraint; chiplet overhead not justified
- Co-packaged optics (CPO) at 1.6T - 3.2T — mixed; both Fotonix monolithic and chiplet/hybrid paths active in production
- Optical I/O chiplets for AI scale-up (UCIe optical) — chiplet wins by definition (Ayar Labs TeraPHY); the photonic chiplet must mate with diverse host chiplets at the package boundary
- Long-haul coherent / metro / DCI — monolithic SiPh dominates because optical performance and DSP integration matter more than chiplet flexibility
- AI-fabric scale-out (rack-to-rack) — TBD; depends on whether the network ASIC is itself a CPO recipient (favors chiplet) or hosts pluggables (favors monolithic)
The structural moat for GF Fotonix is on the monolithic side — high-volume pluggables and CPO programs that need lowest BOM and best power-per-bit.
The structural risk for GF Fotonix is on the chiplet side — every UCIe optical chiplet design that succeeds is a port that does not need a Fotonix monolithic die.
6. Where Fotonix-monolithic and chiplet meet — Ayar Labs
Ayar Labs is structurally in both camps:
- Ayar Labs TeraPHY chiplet is itself fabricated on GF Fotonix — meaning the chiplet, even though it is delivered to customers as a chiplet, is internally a monolithic SiPh die
- The chiplet boundary is at the host-package level, not at the die level
This means GF Fotonix wins both architecture choices when Ayar Labs wins a design slot. The architectural distinction is at the system level (chiplet vs monolithic at host package), not at the photonic-die level.
The same applies to Marvell’s optical engine architecture: the photonic die is on Fotonix (monolithic CMOS+photonics for the driver/photodiode integration); the DSP is a separate die on TSMC; the package is multi-die. Marvell at the system level is “chiplet”; at the photonic-die level is monolithic Fotonix.
7. Time-to-market dynamics
| Path | Time to first silicon | Time to volume | Notes |
|---|---|---|---|
| Monolithic Fotonix tape-out (productized PDK customer) | 6-9 months | 12-24 months | Standard PDK fab cycle |
| Monolithic Fotonix tape-out with process modification | 12-18 months | 18-36 months | Slot-waveguide LWLG / SOH NLM path |
| Chiplet integration of an existing photonic die | 3-6 months | 6-12 months | Faster because each die is reused |
| Greenfield chiplet design with new photonic die | 12-18 months | 24-36 months | All risks compound |
The monolithic path is slower per-design but faster in aggregate for a customer that taps the platform repeatedly. Each new product generation reuses the validated Fotonix process; only the photonic + CMOS layout changes. This is why captive-volume customers (Marvell, Broadcom, NVIDIA) prefer monolithic for the bulk of their portfolio and reserve chiplet for boundary cases (UCIe optical I/O, custom AI accelerator scale-up).
8. Strategic implications for GFS
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GF’s monolithic moat is real but narrowing. Tower’s 300mm SiPh port + CPO foundry positioning, TSMC’s wafer-bond-based hybrid SiPh + CoWoS, and the chiplet ecosystem are all actively competing. GF needs to keep Fotonix at the leading edge of process modifications (slot waveguides for polymers, advanced modulator topologies, packaging features) to maintain customer commitment.
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The AMF acquisition adds chiplet-friendly capacity. AMF’s 200mm Singapore line is a natural home for chiplet-architecture customers who want their photonic die fab’d separately from their CMOS — the same customers a chiplet-friendly TSMC SiPh approach would target. GF now has both monolithic-Malta and chiplet-friendly-Singapore in one portfolio.
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The EO-polymer integration play is monolithic-coded. LWLG’s commercial path runs through monolithic Fotonix — slot waveguides + BEOL polymer fill on the same die as the driver/TIA. NLM’s first-gen path is on AMF (200mm, photonic-only, more chiplet-friendly), reflecting NLM’s slightly different commercial positioning.
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The 400 Gb/s per lane CoE charter is fundamentally a monolithic / advanced-process-integration program. The materials being researched (EO polymers, TFLN, POH) are integration challenges that benefit from monolithic process control more than chiplet packaging.
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The chiplet risk is asymmetric. GF doesn’t lose much if chiplet wins — Ayar Labs’ TeraPHY is also fabbed at Fotonix, just delivered as a chiplet. GF only loses if chiplet wins and the photonic die migrates to TSMC SiPh / Tower PH18 / AMF (now GF) / IBM. The portfolio bridge across all four scenarios is what makes GF’s photonics position robust.
9. Open audit items
- ⚠ Quantitative power-per-bit comparison — Fotonix monolithic vs TSMC SiPh+CoWoS vs Ayar Labs UCIe — needs primary OFC/ECOC paper citation.
- ⚠ BOM cost-per-port comparison at 1.6T pluggable scale — industry estimates exist but not primary-sourced GF/Tower/TSMC numbers.
- ⚠ Yield comparison for very large CPO dies — GF’s yield position vs Tower’s CPO foundry vs TSMC.
- ⚠ Fotonix die-size limits — what is the maximum reticle stitch / chip-on-wafer area Fotonix supports?
10. Cross-references
- Fotonix process overview — the monolithic platform
- AMF Singapore acquisition — the chiplet-friendly 200mm complement
- Fotonix PDK customers — Ayar Labs, Marvell as the bridge customers
- competitors — Tower / TSMC / Intel / IMEC competitive set