GF Fotonix — process overview (45SPCLO + 9WG)

Updated: 2026-04-29 Status: ✓ Verified via GF Newsroom press releases, GF technology pages, CMC Microsystems PDK pages, and OFC / CLEO conference proceedings, except where flagged. Cross-references: Process roadmap · Fotonix PDK customers · AMF Singapore acquisition · competitors

Executive summary

GF Fotonix is GlobalFoundries’ branded silicon-photonics platform. Marketing-wise “Fotonix” is the umbrella; underneath it sit two productized process nodes: the 45SPCLO (45 nm Silicon Photonics CMOS Logic Optical) on 300mm SOI wafers, and the 9WG (9-Waveguide) variant built on a 90 nm SOI base. Fotonix is the first commercially available foundry process to integrate 300 mm-class silicon photonics with 300 GHz-class RF-CMOS on a single monolithic die (GF March 2022 launch press release). The platform is fabricated at GF’s Fab 8 in Malta, NY (GF Newsroom).

The hero performance metric GF cites is 0.5 Tbps per fiber — claimed as the highest data rate per fiber demonstrated on a commercially available SiPh foundry process (GF technology page). This combines wavelength-division multiplexing across multiple lanes per fiber, monolithic SiGe-class drivers/TIAs, and an integrated polarization-management photonic library.

The platform’s commercial moat is the monolithic combination of CMOS + photonics: drivers, transimpedance amplifiers, photonic modulators, photodetectors, and waveguides all on the same die, eliminating the chip-to-chip bond-wire / interposer parasitics that constrain hybrid SiPh implementations. Tower PH18 (Newport Beach 200mm) and recent 300mm port and Intel SiPh (internal-only) are the closest comparables — Fotonix’s open-foundry productization at 300mm SOI scale is the differentiator.

1. Node architecture

1.1 Fotonix 45SPCLO — the flagship 300mm node

Parameter	Value	Source
Wafer size	300 mm	GF technology page ✓
Substrate	Silicon-on-Insulator (SOI)	CMC 45SPCLO PDK page ✓
CMOS node	45 nm RF-SOI base; 40 nm minimum gate-only image	CMC ✓
Core voltages	0.9 V / 1.0 V	CMC ✓
BEOL metallization	9 levels	CMC ✓
Far-BEOL feature	V-groove integration for fiber attach	CMC ✓
PDK	45SPCLO_v1.0_1.0a (photonic + electronic libraries)	CMC ✓
Fab location	Malta, NY (Fab 8)	GF blog ✓
Hero data rate	0.5 Tbps per fiber	GF tech page ✓
CMOS RF performance	300 GHz-class RF-CMOS	GF press release Mar 2022 ✓

The monolithic integration claim is what GF leans into: a single die contains the photonic devices (modulators, photodetectors, waveguides, couplers, polarization splitter-rotators, phase shifters) plus the RF-CMOS transistors that drive them and that read them out. In a hybrid SiPh approach (e.g., POET Optical Interposer, Ayar Labs’ early architecture before its UCIe chiplet shift) the modulator/photodetector and the driver/TIA are separate dies bonded together; in Fotonix they are lithographically co-fabricated.

1.2 Fotonix 9WG — the 90 nm 9-waveguide variant

Parameter	Value	Source
Platform	90 nm SOI	CMC 9WG PDK ✓
Starting substrate	2 µm BOX, 170 nm SOI for CMOS and photonic devices	CMC ✓
Mask levels	48 total (40 with hybrid photonics-only option)	CMC ✓
BEOL	7 levels (6 Cu + 1 Al), 1P7M with LVT configuration	CMC ✓
Far-BEOL feature	V-groove integration + Ge EPI integration	CMC ✓
PDK	90SIPH-9WG	CMC ✓

The 9WG designation refers to the 9-waveguide offering — a broad photonic device library on the 90 nm SOI platform optimized for the cost-sensitive end of GF’s photonics customer set (5G fronthaul/backhaul, datacom, automotive LiDAR, sensing). The exact list of 9 waveguide types is not enumerated on the public CMC page; ⚠ a follow-up to GF’s design-rule manual is needed to catalogue them definitively, but they encompass single-mode strip / rib / partial-rib silicon waveguides at 1310 nm and 1550 nm, low-loss silicon-nitride routing waveguides for thermal-insensitive segments, and germanium-photodetector waveguides.

The 9WG node is positioned as the higher-volume / lower-feature-density complement to the more aggressive 45SPCLO — Lightmatter is publicly identified as a customer for the 9WG variant for tensor-core integration (SemiAnalysis).

2. Photonic device library

The 45SPCLO PDK ships a productized photonic element library, validated for tape-out in customer designs:

Device class	Implementation	Use case
Modulators	Mach-Zehnder (MZM), micro-ring (MRM), ring-assisted Mach-Zehnder (RAMZM)	High-speed PAM4/coherent at 100-200 G/lane; the MRM path is the wavelength-division-friendly variant; RAMZM is the bandwidth-extended next-gen GF added in the 2024 Fotonix refresh
Photodetectors	Germanium-on-Si	C-band and O-band PDs; integrated with TIA inputs in the same die
Edge couplers	Spot-size converters	Fiber-to-chip coupling at die edge; pairs with V-groove for passive alignment
Grating couplers	Single-polarization and 2-D polarization-diversity gratings	Wafer-level test and alternative fiber-attach
Polarization splitter-rotator (PSR)	On-die	Polarization management without off-chip components
Phase shifters	Thermo-optic, carrier-depletion	Tuning, biasing, and active modulation
Waveguides	Strip Si, rib Si, partial-rib Si, low-loss SiN routing, Ge-PD waveguides	Routing + mode conversion

(Library composition per CMC 45SPCLO page and GF Fotonix next-gen blog ✓.)

The “next-generation Fotonix” 2024 update — disclosed via GF Newsroom and OFC 2024 — extended the modulator portfolio specifically to include MRM and RAMZM topologies, supporting bandwidth upgrades beyond the original MZM-only modulator slot (GF blog, OFC 2024 paper Th3H.2) ✓.

3. Electronic integration on the same die

The defining structural choice of 45SPCLO is that the photonic and electronic devices share a die. The CMOS device library on the 45SPCLO node includes:

300 GHz-class RF-CMOS transistors (FETs), suitable for 100-200 G/lane modulator drivers and TIAs without a separate SiGe BiCMOS die ✓
Precision passives: resistors, capacitors, inductors
CMOS photodiodes (in addition to the Ge photodetectors)
ESD protection circuitry

This is the structural difference vs Tower PH18 (which is fundamentally a 200mm photonic-only process; Tower’s recent CPO foundry and 300mm port narrow the gap but Tower’s RF-CMOS integration is not as deep as GF’s RF-SOI heritage — see competitors) and Intel SiPh (monolithic but internal-only, not a merchant foundry).

The trade-off: monolithic CMOS+photonics introduces process-flow tension between thermal budgets that suit photonics (high-temperature in-process anneals improve waveguide loss) and thermal budgets that suit advanced CMOS (low-temperature post-gate steps preserve transistor performance). GF’s 45SPCLO has solved this by anchoring on a 45 nm node — old enough to have headroom on transistor thermal budget, modern enough to deliver the ~300 GHz RF performance customers need for 200 G/lane PAM4. ◐ (technical reasoning consistent with angel-tech foundry presentation and OFC 2024 paper.)

4. Packaging & fiber attach

The Fotonix process integrates far-BEOL V-groove etching for fiber attach directly into the wafer flow (CMC PDK page) ✓. This is significant because:

It removes a discrete V-groove submount or a separate die-attach step from the back-end packaging
It enables passive-alignment fiber attachment at wafer level — the V-groove geometry mechanically aligns the fiber to the spot-size converter / edge coupler within the lithographic-tolerance budget
It supports both edge coupling (V-groove + edge coupler) and vertical coupling (grating coupler) packaging paths from the same die

The platform also supports both on-die integrated lasers (an advanced packaging option) and off-package laser sources (the more common production configuration where a CW comb laser or external light source feeds the photonic die from off-chip) (GF technology page) ✓.

For co-packaged optics (CPO), GF separately announced co-packaging capabilities aligned with the AI-cluster CPO roadmap (Broadcom Tomahawk-Optical / Marvell Teralynx photonics, NVIDIA Quantum-X / Spectrum-X) — this complements but is distinct from the Fotonix SiPh process node. ⚠ Specific GF CPO substrate technology (interposer, glass, organic) not fully primary-sourced in this audit.

5. PDK and EDA support

The Fotonix PDK (currently shipping 45SPCLO_v1.0_1.0a per CMC) is supported by:

Cadence — Virtuoso integration ✓
Synopsys — co-design flow + Photonic Solutions ✓
Ansys — Lumerical photonic device simulation, certified for Fotonix per Ansys investors release ✓
Luceda — IPKISS-based PDK flow ⚠ (validated for adjacent SilTerra route per LWLG-Luceda-SilTerra disclosure; GF-Luceda specific status to verify)
GDSFactory — open-source PDK flow with Lightwave Logic polymer-modulator integration live as of 2026-03-16 ✓ (Stocktitan LWLG-GF release)
Enosemi — silicon-validated electronic-photonic design IP available in the Fotonix platform per their March 2025 announcement ✓

The PDK has been rev’d through multiple major releases since the March 2022 launch; the precise rev history is not all publicly catalogued but the v1.0 designation on the current CMC PDK indicates GF treats v1.0 as the productization milestone.

6. Yield and process maturity

GF claims Fotonix is in high-volume manufacturing — the only pure-play foundry with 300mm monolithic SiPh in HVM (GF technology page) ✓. Specific yield numbers are not publicly disclosed; ⚠ the most reliable proxy for yield maturity is customer commitment — Marvell shipping Inphi-lineage SiPh products through Fotonix, Ayar Labs scaling to “thousands of engineering samples” and committing to volume between 2026-2028, and Lightmatter, PsiQuantum, and NVIDIA all sourcing from Fotonix is signal that yield is at production-acceptable levels. (See Fotonix PDK customers for the full customer list with citations.)

The OFC 2024 invited paper “Latest Progress and Challenges in 300 mm Monolithic Silicon Photonics Manufacturing” (Optica DOI) ✓ is the most authoritative GF technical disclosure on Fotonix yield and process maturity; the CLEO 2024 invited paper “300-mm monolithic CMOS silicon photonics foundry technology” (Optica DOI) ✓ is the companion overview paper.

7. Where Fotonix sits in the AI-photonics value chain

Fotonix is the foundry layer for the AI-photonics buildout. It does not own modulator material chemistry (LWLG, NLM provide that), it does not design transceivers (Marvell, Broadcom, Coherent, Lumentum do that), and it does not run hyperscaler networks (Microsoft, Google, Meta, Amazon do that). What it does is sit at the single fabrication-cost node that every monolithic-SiPh design must traverse.

The strategic implications:

High switching cost — once a customer’s design is silicon-validated on Fotonix, moving to Tower PH18 / TSMC SiPh / Intel SiPh requires re-tape-out, re-PDK-validation, re-qualification — typically 12-24 months of work
Capacity is rivalrous — every wafer slot booked by NVIDIA / Marvell / Broadcom is a slot not available to LWLG / NLM / Ayar Labs
Technology customer-pull — modulator-IP companies (LWLG, NLM) are materially better off if GF Fotonix is the dominant SiPh PDK because customers will fab on the foundry where the most production-validated photonic libraries already live, and that creates a network effect that benefits LWLG more than NLM in the near term given LWLG’s earlier integration date

The AMF Singapore acquisition (Nov 17 2025) extends this footprint with a complementary 200mm node — see AMF Singapore acquisition.

8. Open audit items

⚠ Definitive enumeration of the 9 waveguide types in the 9WG PDK — GF design-rule manual access required.
⚠ Yield and defect-density disclosure — likely never public; best proxy remains customer commitment cadence.
⚠ Wafer-output capacity at Fab 8 dedicated to Fotonix — not separately disclosed.
⚠ CPO substrate / glass-substrate specifics — GF’s CPO offering technical details not fully primary-sourced.
⚠ 45SPCLO PDK rev history — only v1.0_1.0a publicly listed; intermediate revisions not catalogued.

Cross-references

Process roadmap — Fotonix 1.0 → next-gen evolution
Fotonix PDK customers — who is on the platform
AMF Singapore acquisition — the 200mm complement
Monolithic vs chiplet — competitive positioning
Patents overview — IP layer